1. Field of the Invention
The present invention relates to a plasma processing apparatus, and more particularly to a dry etching apparatus.
2. Description of the Background Art
FIG. 21 is a sectional view conceptually showing an ECR (Electron Cycrotron Resonance) etching apparatus which is a kind of a plasma processing apparatus according to the prior art. In a plasma production chamber 1, a plasma is produced from a process gas by a microwave 19. The plasma is sent to a reaction chamber 2. A wafer 7 biased with a RF power obtained from RF power feeding means 8 is exposed to the plasma.
There are various parameters to control an etching process of the ECR etching apparatus. Examples of the parameters include a shape and a position of an ECR region represented by an ECR face 5 (which also depend on a magnetic field given by a main coil 4a and a mirror coil 4b), the microwave 19, a method for electrostatically chucking the wafer 7, a pressure of the process gas, and the like.
It has become harder to implement etching having higher anisotropy, selectivity and uniformity with higher integration and fineness of a device. In many cases, existing etching parameters are not enough to implement the etching having higher anisotropy, selectivity and uniformity. In recent years, anomalies in an etching shape caused due to charge-up (hereinafter referred to as "charge-up shape anomalies") have been notable as a problem of impeding fineness.
FIGS. 22 and 23 are enlarged sectional views for explaining the charge-up shape anomalies in a vicinity of a surface of a semiconductor wafer 101, and showing behaviors of ions (indicated at "+" around which a circle is put) and electrons (indicated at "-" around which a circle is put) obtained when performing fine pattern etching of the semiconductor wafer 101 using plasma etching.
In FIG. 22, a SiO.sub.2 film 13, a Si film 14 and a resist pattern 15 are sequentially formed on the surface of the semiconductor wafer 101. By using the resist pattern 15 as a mask, etching is performed. With progress of the etching, both the ions and the electrons are incident on a surface of the resist pattern 15. Consequently, electrical neutrality can be kept.
In a fine pattern 16, the ions are incident perpendicularly to the surface of the semiconductor wafer 101. Therefore, the ions do not collide with a side wall 17 of the fine pattern 16 but reach a bottom face 18 of the fine pattern 16. On the other hand, the electrons have no directionality and are also injected into the side wall 17. Therefore, it is hard for the electrons to reach the bottom face 18.
As shown in FIG. 22, when a conductive film such as the Si film 14 is etched, the ions incident on the bottom face 18 and the electrons incident on the side wall 17 are recombined and neutralized in the Si film 14. Consequently, the electrical neutrality can be kept. However, when the etching progresses so that the bottom face 18 is moved downward and an insulating film such as the SiO.sub.2 film 13 is exposed as shown in FIG. 23, the ions incident on the bottom face 18 and the electrons incident on the side wall 17 are not neutralized so that the bottom face 18 is positively charged up. On the other hand, the side wall 17 is negatively charged up by the electrons incident thereto.
Accordingly, an orbit of an ion incident on the bottom face 18 is curved by repulsion of positive electric charges on the bottom face 18 which has been positively charged up and attraction on the side wall 17 which has been negatively charged up. Therefore, the ions locally are incident on an interface of the Si film 14 and the SiO.sub.2 film 13 so that a so-called notch is generated (a notch quantity is shown by "A" in FIG. 23).